1. Field of the Invention
The present disclosure relates to an oscillator circuit.
2. Description of the Related Art
FIG. 5 shows the circuit composition of an oscillator circuit according to the related art. As shown in FIG. 5, in this oscillator circuit, a built-in oscillator 1 generates a clock signal with a frequency on the order of several hundreds of 1 MHz (megahertz). This clock signal is supplied to a frequency divider circuit 2. The frequency divider circuit 2 converts the clock signal into a ½ frequency signal, a ¼ frequency signal, a ⅛ frequency signal, and a 1/16 frequency signal, and supplies each divided frequency signal to a frequency selection circuit 3. The frequency selection circuit 3 selects one of the divided frequency signals according to a selection signal received from a terminal 4, and outputs the selected frequency signal from a terminal 5 as a main clock signal. The main clock signal is supplied to a CPU (which is not illustrated), for example. The selection signal is changed according to the mode of operation of the CPU.
Further, a low-speed clock oscillator 6 generates a low-speed clock signal with a frequency on the order of several tens of 1 kHz (kilohertz). This low-speed clock signal is output from a terminal 7 as a sub-clock signal. The sub-clock signal is supplied to a timer (which is not illustrated), for example.
FIG. 6 shows the circuit composition of another oscillator circuit according to the related art. As shown in FIG. 6, in this oscillator circuit, a low-speed clock oscillator 11 generates a low-speed clock signal with a frequency on the order of several tens of 1 kHz. This low-speed clock signal is output from a terminal 12 as a sub-clock signal. The sub-clock signal is supplied to a timer (which is not illustrated), for example.
Further, the sub-clock signal is supplied to a PLL (phase locked loop) 13. The PLL 13 generates a clock signal with a frequency on the order of several hundreds of 1 MHz, and this clock signal is synchronized with the sub-clock signal. The clock signal is supplied to a frequency divider circuit 14. The frequency divider circuit 14 converts the clock signal into a ½ frequency signal, a ¼ frequency signal, a ⅛ frequency signal, and a 1/16 frequency signal, and supplies each divided frequency signal to a frequency selection circuit 15.
The frequency selection circuit 15 selects one of the divided frequency signals according to a selection signal received from a terminal 16, and outputs the selected frequency signal from a terminal 17 as a main clock signal. The main clock signal is supplied to a CPU (which is not illustrated), for example. The selection signal is changed according to the mode of operation of the CPU.
In the meanwhile, there is known a clock controller system which includes a clock control circuit, a first oscillator circuit used for low-speed operation, and a second oscillator circuit used for high-speed operation. For example, refer to Japanese Laid-Open Patent Publication No. 08-272478.
In the known clock controller system, the clock control circuit performs on/off control of the two oscillator circuits according to the operating conditions of the system. A clock signal generated by the first oscillator circuit is supplied to a CPU and a CPU peripheral circuit respectively via a selector as a system clock signal in a low-speed operation mode.
At this time, the second oscillator circuit is kept in a halt state by an oscillation control signal from the clock control circuit.
In the related art oscillator circuit of FIG. 5, the oscillating frequency of the built-in oscillator 1 is constant even when the main clock signal is in a low-speed operation mode, so that it is difficult to reduce power dissipation of the related art oscillator circuit. Further, the related art oscillator circuit has a problem that the built-in oscillator 1 and the low-speed clock oscillator 6 must be provided independently of each other.
In the related art oscillator circuit of FIG. 6, the oscillating frequency of the PLL 13 is constant even when the main clock signal is in a low-speed operation mode, and it is difficult to reduce power dissipation of the related art oscillator circuit. Further, the related art oscillator circuit has a problem that the PLL 13 and the low-speed clock oscillator 11 must be provided independently of each other.